This invention relates to integrated circuit (IC) fabrication processes, and in particular to methods and test circuits for identifying and locating defective vias and contacts during IC fabrication process.
Integrated Circuit (IC) devices typically include numerous electrical and/or electronic elements that are fabricated on, for example, silicon wafers to perform a particular function. The sequence of steps that occur in the course of manufacturing an IC device can be grouped into two phases: 1) the design phase, and 2) the fabrication phase.
The design phase begins by deciding upon the desired functions and necessary operating specifications of the IC device. The IC device is then designed from the xe2x80x9ctop downxe2x80x9d; that is, large functional blocks are first identified, then sub-blocks are selected, and then the logic gates needed to implement the sub-blocks are chosen. Each logic gate is designed through the appropriate connection of, for example, transistors and resistors. The logic gates and other circuit components are then combined to form schematic diagrams. After the various levels of design are completed, each level is checked to insure that correct functionality is achieved, and then test vectors are generated from the schematic diagrams. Next, the circuit is laid out. A layout consists of sets of patterns that will be transferred to the silicon wafer. These patterns correspond to, for example, the formation of transistors and interconnect structures. The layout is designed from the xe2x80x9cbottom upxe2x80x9d; for example, basic components (e.g., transistors) are first laid out, then logic gates are created by interconnecting appropriate basic components, forming the logic gates into sub-blocks, and finally connecting appropriate sub-blocks to form functional blocks. Power busses, clock-lines, and input-output pads required by the circuit design are also incorporated during the layout process. The completed layout is then subjected to a set of design rule checks and propagation delay simulations to verify that a correct implementation of the circuit design has been achieved. After this checking procedure, the layout is used to generate a set of masks that are used during the fabrication phase to specify the circuit patterns on the silicon wafer.
Specifically, the fabrication phase includes a sequence of process steps during which the set of masks are used to transfer the layout patterns onto a silicon wafer using photolithographic and film formation processes. The process parameters (e.g., temperature, pressure, deposition rates and times, etch rates and times) associated with the process steps are typically developed and refined during an initial development stage. These refined process parameters are then used to produce a final fabrication process that is used during IC production runs.
There may be defects in the fabrication process. In order to identify the precise structural nature of defects caused by non-optimal process parameters, test structures are formed on the wafer. By studying these test structures, it is possible to improve and refine the fabrication process. These test structures are necessary as the physical nature of these defects cannot be discerned from output data of the ICs. Specifically, defects in the ICs produce functional errors in the output data. These functional errors provide little or no information to identify the physical structure causing the defect. As explained in detail below, even with test structures, information about the exact location and nature of the defect is still not readily obtainable. Thus, failure analysis remains difficult and time consuming.
One type of structure in a wafer that needs to be tested is contacts and vias. Currently, they are tested by measuring the resistance of a long chain comprising a few thousand connected vias/contacts. Typically, a tester having a resistance measuring device is used for the measurement. A prober of the test system provides connection between the tester and the chain under test. An open via/contact can be easily identified because the measured resistance of the chain is much higher than the expected resistance for a chain of regular vias/contacts. However, it is very difficult to identify a high resistance via/contact that has a few hundred ohms (as opposed to a regular via that has a resistance of about 10 ohms) in a long chain of vias/contacts. This is because the resistance of a chain of non-defective vias/contacts is more than ten thousand ohms, and has a normal variation of resistance of 5% to 10%. The resistance of such a high resistance via/contact is within the xe2x80x9cnoisexe2x80x9d variation of the resistance of a long chain.
One way to increase the accuracy of resistance measurement is to reduce the number of vias in a chain. For example, if a chain contains about one hundred vias, the resistance of the chain is approximately one thousand ohms. Thus, the presence of a high resistance via (having a resistance of, say, two hundred ohms) in the chain can be easily detected because the resistance of the chain is increased by 20%, which is beyond the noise level. As the chain becomes shorter, more chains need to be tested so as to cover the same number of vias. This means that the prober needs to be mechanically moved many times from one via chain to another. The problem of this approach is that it could slow down the testing process because of the increasing number of slow mechanical operations caused by short via chains.
Another test structure is the so called xe2x80x9cdrop inxe2x80x9d structure. FIG. 1 is a plan view showing a conventional semiconductor test wafer 100 including circuit ICs (shown as reference numeral 110) and conventional drop-in test structures (shown as reference numerals 112). Conventional test structure 112 is used to detect defects associated with the various conductive materials that are fabricated during the various process steps.
One problem of the drop-in structure is that they are relatively large. It is known that wafer area is very valuable and expensive. Thus, it is not desirable to place on production wafers large drop-in test structures for monitoring contacts and vias.
What is needed is an improved test circuit and method that can readily and reliably identify and isolate fabrication defects in vias and contacts, thereby facilitating rapid development and refinement of the fabrication process steps necessary to manufacture IC devices.
The present invention is directed to a method and a test circuit that provide rapid identification of process problems, detect defects down to less than a few parts-per-million level, and identify the precise location of any defects, thereby facilitating rapid failure analysis. A tester having a resistance measurement device is used to measure the resistance of chains of vias. In the present invention, one or more circuit arrangements are fabricated on a semiconductor wafer. The arrangement contains a plurality of chains of connected vias, contacts and a plurality of decoders. Each decoder is associated with one of the via chains. Each decoder also has a set of address lines. When a predetermined address is presented to the address line, the decoder causes its associated via chain to be connected to the resistance measurement device. In order for the via chains to be measured one at a time, each decoder has a unique predetermined address. By sequentially applying different predetermined addresses to the decoders, all the via chains can be sequentially connected to the resistance measurement device so that the resistance of all the chains can be individually measured.
In one embodiment, a Kelvin resistance measurement device is used to measure the resistance of the chains. One advantage is that the parasitic resistance in the supporting circuit elements, probe card, and cable can be rendered negligible.
In another embodiment, the decoders are designed to use N-channel transistors only. These transistors can be fabricated under most CMOS processes without the need to modify the implant data of the design. As a result, many foundries can use the test circuit of the present invention to improve their fabrication processes.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.